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Shared from Digital Logic - 4 on Dec 10, 2010 7:00 AM

In the figure given below, U₁ is a 4-bit synchronous centre with synchronous clear. Q₀ is the LSB and Q₃ is the MSB of the output.

The circuit represents a

mod 2 counter

mod 3 counter

mod 4 counter

mod 5 counter

Please type your answer before submitting.

Debashis Das Chakla

The answer is mod 4 as the count start from 0 and it stops until it clear(3)-->0,1,2,3=4 count-->mod 4

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